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White Electronic Designs
WV3HG64M72EER-D6
ADVANCED*
512MB - 64Mx72 DDR2 SDRAM REGISTERED DIMM, w/PLL
FEATURES
Registered 240-pin, dual in-line memory module Fast data transfer rates: PC2-6400*, PC2-5300*, PC2-4200 and PC2-3200 Utilizes 800*, 667*, 533 and 400 MT/s DDR2 SDRAM components VCC = VCCQ = 1.8V 0.1V VCCSPD = 1.7V to 3.6V JEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture Multiple internal device banks for concurrent operation Supports duplicate output strobe (RDQS/RDQS#) Write Latency = Read Latency 1tck Programmable CAS# latency (CL): 3, 4, 5* and 6* Adjustable data-output drive strength On-die termination (ODT) 7.8s average periodic refresh interval Posted CAS# latency: 0, 1, 2, 3 and 4 Serial Presence Detect (SPD) with EEPROM Auto & Self Refresh (8k/64ms refresh) Gold edge contacts RoHS compliant Package option * 240 Pin DIMM * PCB - 30.00mm (1.181") TYP
DESCRIPTION
The WV3HG64M72EER is a 64Mx72 Double Data Rate DDR2 SDRAM high density module. This memory module consists of nine 64Mx8 bit with 4 banks DDR2 Synchronous DRAMs in FBGA packages, mounted on a 240-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. NOTE: Consult factory for availability of: * Vendor source control options * Industrial temperature option
OPERATING FREQUENCIES
PC2-3200 Clock Speed CL-tRCD-tRP
* Consult factory for availability
PC2-4200 266MHz 4-4-4
PC2-5300* 333MHz 5-5-5
PC2-6400* 400MHz 6-6-6
200MHz 3-3-3
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PIN CONFIGURATION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbol VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS RESET# NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8# DQS8 VSS CB2 CB3 VSS VCC CKE0 VCC NC NC VCC A11 A7 VCC A5 Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Symbol A4 VCC A2 VCC VSS VSS VCC NC VCC A10/AP BA0 VCC WE# CAS# VCC NC NC VCC VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS DQ58 DQ59 VSS SDA SCL Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Symbol VSS DQ4 DQ5 VSS DM0/DQS9 NC/DQS9# VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1/DQS10 NC/DQS10# VSS NC NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2/DQS11 NC/DQS11# VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3/DQS12 NC/DQS12# VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8/DQS17 NC/DQS17# VSS CB6 CB7 VSS VCC NC VCC NC NC VCC A12 A9 VCC A8 A6 Pin No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Symbol VCC A3 A1 VCC CK0 CK0# VCC A0 VCC BA1 VCC RAS# CS0# VCC ODT0 A13 VCC VSS DQ36 DQ37 VSS DM4/DQS13 NC/DQS13# VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5/DQS14 NC/DQS14# VSS DQ46 DQ47 VSS DQ52 DQ53 VSS NC NC VSS DM6/DQS15 NC/DQS15# VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7/DQS16 NC/DQS16# VSS DQ62 DQ63 VSS VCCSPD SA0 SA1 2
WV3HG64M72EER-D6
ADVANCED
PIN NAMES
Pin Name A0-A13 BA0,BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS17 DQS0#-DQS17# DM0 - DM8 ODT0 CK0,CK0# CKE0 CS0# RAS# CAS# WE# RESET# VCC VSS SA0-SA2 SDA SCL VREF VCCSPD NC Function Address Inputs SDRAM Bank Addresses Data Input/Output Check Bits Data strobes Data strobes complement Data Masks On-die termination control Clock Inputs Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Register Reset Input/PLL OE Core and I/O Power (1.8V) Ground SPD address SPD Data Input/Output Serial Presence Detect(SPD) Clock Input Input/Output Reference Voltage SPD Power Spare pins, No connect
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FUNCTIONAL BLOCK DIAGRAM
RCS0# DQS0 DQS0# DM0/DQS9 NC/DQS9#
DM/ RDQS NU/ CS# DQS DQS# RDQS#
WV3HG64M72EER-D6
ADVANCED
DQS4 DQS4# DM4/DQS13 NC/DQS13#
DM/ RDQS NU/ CS# DQS DQS# RDQS#
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1# DM1/DQS10 NC/DQS10#
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS5 DQS5# DM5/DQS14 NC/DQS14#
DM/ RDQS NU/ CS# DQS DQS# RDQS#
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DM/ RDQS
NU/ CS# DQS DQS# RDQS#
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS2# DM2/DQS11 NC/DSS11#
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS6 DQS6# DM6/DQS15 NC/DQS15#
DM/ RDQS NU/ CS# DQS DQS# RDQS#
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DM/ RDQS
NU/ CS# DQS DQS# RDQS#
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3# DM3/DQS12 NC/DSS12#
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS7 DQS7# DM7/DQS16 NC/DQS16#
DM/ RDQS NU/ CS# DQS DQS# RDQS#
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DM/ RDQS
NU/ CS# DQS DQS# RDQS#
Serial PD SCL WP A0 A1 A2 SDA
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQS8# DM8/DQS17 NC/DSS17#
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
SA0 SA1 SA2
DM/ RDQS
NU/ CS# DQS DQS# RDQS#
VCCSPD VCC/VCCQ VREF VSS
Serial PD DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAMs
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS0# BA0 - BA1 A0 - A13 RAS# CAS# WE# CKE0 ODT0 RESET#** PCK7** PCK7#**
1:2 R E G I S T E R
RST#
CK0
RCS0# : DDR2 SDRAMs RBA0 - RBA1 : DDR2 SDRAMs RA0 - RA13 : DDR2 SDRAMs RRAS# : DDR2 SDRAMs RCAS# : DDR2 SDRAMs RWE# : DDR2 SDRAMs RCKE0 : DDR2 SDRAMs RODT0 : DDR2 SDRAMs
CK0# RESET#
P L L
OE
PCK0-PCK6, PCK8, PCK9
CK : DDR2 SDRAMs CK# : DDR2 SDRAMs
PCK0#-PCK6#, PCK8#, PCK9# PCK7 CK : Register PCK7# CK# : Register
NOTE: All resistor values are 22 ohms unless otherwise specified. **RESET#, PCK7 and RCK7# connects both registers. Other signals connect to one of two registers.
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DC OPERATING CONDITIONS
All voltages referenced to VSS Parameter Supply Voltage I/O Reference Voltage I/O Termination Voltage SPD Supply Voltage Symbol VCC VREF VTT VCCSPD Min 1.7 0.49 x VCC VREF-0.04 1.7 Typical 1.8 0.50 x VCC VREF -
WV3HG64M72EER-D6
ADVANCED
Max 1.9 0.51 x VCC VREF+0.04 3.6
Unit V V V V
Notes 3 1 2
Notes: 1 VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the
DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 3. VCCQ of all IC's are tied to VCC.
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VIN, VOUT TSTG Parameter Voltage on VCC pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Input leakage current: Any input 0VIL
CAPACITANCE
TA = 25C, f = 100MHz Parameter Input Capacitance: (A0~A13, BA0~BA1, RAS#, CAS#, WE#) Input Capacitance: (CKE0), (ODT0) Input Capacitance: (CS0#) Input Capacitance: (CK0, CK0#) Input Capacitance: (DM0~DM8), DQS0~DQS17) Input/Output Capacitance: (DQ0 ~ DQ63), (CB0 ~CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 COUT1 Min 11 11 11 10 6.5 6.5 Max 12 12 12 11 8 8 Units pF pF pF pF pF pF
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Parameter Operating Case Temperature (Commercial) Symbol TOPER Rating 0 to +85C
WV3HG64M72EER-D6
ADVANCED
OPERATING TEMPERATURE CONDITION
Units C Notes 1, 2
NOTE: 1. Operation temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2 2. At 0 to +85C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS Parameter Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Symbol VIH(DC) VIL(DC) Min VREF + 0.125 - 0.300 Max VCC + 0.300 VREF - 0.125 Unit V V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS Parameter AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533 AC Input High (Logic 1) Voltage DDR2-667 AC Input High (Logic 0) Voltage DDR2-400 & DDR2-533 AC Input High (Logic 0) Voltage DDR2-667 Symbol VIH(AC) VIH(AC) VIL(AC) VIL(AC) Min VREF + 0.250 VREF + 0.200 Max VREF - 0.250 VREF - 0.200 Unit V V V V
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Includes DDR2 SDRAM components only Symbol ICC0* Proposed Conditions Operating one bank active-precharge current; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W
WV3HG64M72EER-D6
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
806
TBD
665
TBD
534 1,120
403 1,120
Units mA
ICC1*
TBD
TBD
1,255
1,255
mA
ICC2P*
Precharge power-down current; All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1
TBD
TBD
472
472
mA
ICC2Q**
TBD
TBD
670
670
mA
ICC2N**
TBD
TBD
715 670 508
715 670 508
mA mA mA
ICC3P**
TBD TBD
TBD TBD
ICC3N**
Active standby current; All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W Burst auto refresh current; tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Normal
TBD
TBD
850
850
mA
ICC4W*
TBD
TBD
1,480
1,390
mA
ICC4R*
TBD
TBD
1,525
1,390
mA
ICC5B**
TBD
TBD
1,160
1,660
mA
ICC6**
TBD
TBD
72
72
mA
ICC7*
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
TBD
TBD
2,380
2,380
mA
Note: ICC specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different. *: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode. **: Value calculated reflects all module ranks in this operating condition.
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AC CHARACTERISTICS PARAMETER Clock cycle time Clock CL = 6 CL = 5 CL = 4 CL = 3 SYMBOL tCK (6) tCK (5) tCK (4) tCK (3) tCH tCL tHP tJIT tAC tHZ tLZ tDS tDH tDIPW tQHS tQH tDVW tDQSH tDQSL tDQSCK tDSS tDSH tDQSQ tRPRE tRPST tWPRES tWPRE tWPST tDQSS
tIPW tIS tIH tCCD
WV3HG64M72EER-D6
ADVANCED
AC TIMING PARAMETERS & SPECIFICATIONS
806 MIN
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
665 MAX
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
534 MAX 8,000 8,000 8,000 0.55 0.55 125 +450 MIN MAX MIN
403 MAX UNIT ps ps ps ps tCK tCK ps ps ps ps ps
MIN 3,000 3,750 5,000 0.45 0.45
MIN(tCH,tCL)
3,750 5,000 0.45 0.45
MIN(tCH,tCL)
8,000 8,000 0.55 0.55 125 +500 tAC(MAX)
5,000 5,000 0.45 0.45
MIN(tCH,tCL)
8,000 8,000 0.55 0.55 125 +600 tAC(MAX)
CK high-level width CK low-level width Half clock period Clock jitter DQ output access time from CK/CK# Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS DQ and DM input pulse width (for each input) Data hold skew factor DQ...DQS hold, DQS to first DQ to go nonvalid, per access Data valid output window (DVW) DQS input high pulse width DQS input low pulse width DQS output access time from CK/CK# DQS falling edge to CK rising ... setup time DQS falling edge from CK rising ... hold time DQS...DQ skew, DQS to last DQ valid, per group, per access DQS read preamble DQS read postamble DQS write preamble setup time DQS write preamble DQS write postamble Write command to first DQS latching transition
Address and control input pulse width for each input Address and control input setup time Address and control input hold time Address and control input hold time
-125 -450
-125 -500
-125 -600
tAC(MAX) tAC(MIN) 100 225 0.35 340 tHP - tQHS tQH - tDQSQ 0.35 0.35 -400 0.2 0.2 240 0.9 0.4 0 0.35 0.4 WL0.25 0.6 200 275
2
TBD
TBD
tAC(MAX)
tAC(MIN) 100 225 0.35
tAC(MAX)
tAC(MIN) 150 275 0.35
tAC(MAX)
TBD
TBD
Data
TBD TBD
TBD TBD
tCK 450 ps ps ns tCK tCK ps tCK tCK 350 ps tCK tCK ps tCK tCK tCK
tCK ps ps tCK
TBD TBD
TBD TBD
400 tHP - tQHS tQH - tDQSQ 0.35 0.35 -450 0.2 0.2 300 0.9 0.4 0 0.35 0.4 WL0.25 0.6 250 375
2
tHP - tQHS tQH - tDQSQ 0.35 0.35 -500 0.2 0.2
TBD TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD
+400
+450
+500
Data Strobe
TBD
TBD
TBD TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD
1.1 0.6
1.1 0.6
0.6 WL+ 0.25
0.6 WL+ 0.25
TBD TBD TBD TBD
TBD TBD TBD TBD
0.9 0.4 0 0.35 0.4 WL0.25 0.6 250 475
2
1.1 0.6
0.6 WL+ 0.25
* AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. Continued on next page
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AC TIMING PARAMETERS (cont'd)
AC CHARACTERISTICS PARAMETER
ACTIVE to ACTIVE (same bank) command ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay Four Bank Activate period ACTIVE to PRECHARGE command Internal READ to precharge command delay Write recovery time Auto precharge write recovery + precharge time Internal WRITE to READ command delay PRECHARGE command period PRECHARGE ALL command period LOAD MODE command cycle time CKE low to CK,CK# uncertainty REFRESH to Active of Refresh to Refresh command interfal
WV3HG64M72EER-D6
ADVANCED
806 SYMBOL
tRC tRRD tRCD tFAW tRAS tRTP tWR tDAL tWTR tRP tRPA tMRD tDELAY tRFC tREFI tXSNR tXSRD tISXR tAOND tAON tAOFD tAOF tAONPD
665 MAX
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
534 MAX MIN
55 7.5 15 37.5 40 7.5 15 tWR+tRP 7.5 15 tRP+tCK 2 tIS+tCK tIH
403 MAX MIN
55 7.5 15 37.5 40 7.5 15 tWR+tRP 7.5 15 tRP+tCK 2 tIS+tCK tIH
MIN
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
MIN
55 7.5 15 37.5 40 7.5 15 tWR+tRP 7.5 15 tRP+tCK 2 tIS+tCK tIH
MAX
UNIT
ns ns ns ns ns ns ns ns ns ns ns tCK ns
Command and Address
37.5 70,000
37.5 70,000
37.5 70,000
127.5
70,000 7.8
127.5
70,000 7.8
127.5
70,000 7.8
ns s ns tCK ps
Self Refresh
Average periodic refresh interval Exit self refresh to non-READ command Exit self refresh to READ command Exit self refresh timing reference ODT turn-on delay ODT turn-on ODT turn-off delay ODT turn-off
TBD TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD
tRFC(MIN) +10 200 tIS 2 tAC(MIN) 2.5 tAC(MIN) tAC(MIN) +2000 tAC(MIN) +2000 3 8 2 7-AL 2 3 2 tAC(MAX) +1000 2.5 tAC(MAX) +600 2 x tCK+ tAC(MAX) +1000 2.5 x tCK+ tAC(MAX) +1000
tRFC(MIN) +10 200 tIS 2 tAC(MIN) 2.5 tAC(MIN) tAC(MIN) +2000 tAC(MIN) +2000 3 8 2 6-AL 2 3 2 tAC(MAX) +1000 2.5 tAC(MAX) +600 2 x tCK+ tAC(MAX) +1000 2.5 x tCK+ tAC(MAX) +1000
tRFC(MIN) +10 200 tIS 2 tAC(MIN) 2.5 tAC(MIN) tAC(MIN) +2000 tAC(MIN) +2000 3 8 2 6-AL 2 3 2 tAC(MAX) +1000 2.5 tAC(MAX) +600 2 x tCK+ tAC(MAX) +1000 2.5 x tCK+ tAC(MAX) +1000
tCK ps tCK ps ps
TBD TBD TBD
TBD TBD TBD
ODT
ODT turn-on (power-down mode)
TBD
TBD
ODT turn-off (power-down mode) ODT to power-down entry latency ODT power-down exit latency Exit active power-down to READ command, MR[bit12=0] Exit active power-down to READ command, MR[bit12=1] A Exit precharge power-down to any nonREAD command. CKE minimum high/low time
tAOFPD tANPD tAXPD tXARD tXARDS tXP tCKE
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
ps tCK tCK tCK tCK tCK tCK
* AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
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WV3HG64M72EER-D6
ADVANCED
ORDERING INFORMATION FOR D6
Part Number WV3HG64M72EER806D6 WV3HG64M72EER665D6 WV3HG64M72EER534D6 WV3HG64M72EER403D6 Speed 400MHz/800Mb/s 333MHz/667Mb/s 266MHz/533Mb/s 200MHz/400Mb/s CAS Latency 6 5 4 3 tRCD 6 5 4 3 tRP 6 5 4 3 Height* 30.00mm (1.181") TYP 30.00mm (1.181") TYP 30.00mm (1.181") TYP 30.00mm (1.181") TYP
NOTES: * RoHS products. ("G" = RoHS Compliant) * Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x" in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR D6
FRONT VIEW
133.50 (5.256) 133.20 (5.244)
4.0 (0.158) MAX
3.00 (0.118)
(4X)
4.00 (0.158)
(4X) 30.50 (1.201) 29.85 (1.175) 17.80 (0.700) TYP.
5.175 (0.204)
(2X)
PIN 1
1.0 (0.039) TYP. 0.80 (0.032) TYP. 1.50 (0.059) 123.0 (4.843) TYP. 10.00(0.394 ) TYP.
1.37 (0.054) 1.17 (0.046)
PIN 120
BACK VIEW
PIN 240
63.0 (2.480) TYP.
5.0 (0.197) TYP. 55.0 (2.165) TYP.
PIN 121
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
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PART NUMBERING GUIDE
WV3HG64M72EER-D6
ADVANCED
WV 3 H G 64M 72 E E R xxx D6 x x G
WEDC MEMORY DDR 2 GOLD DEPTH BUS WIDTH x8 1.8V REGISTERED SPEED (Mb/s) PACKAGE 240 PIN INDUSTRIAL TEMP OPTION (For commercial leave "blank" for industrial add "I") COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT
August 2006 Rev. 1
10
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
512MB - 64Mx72 DDR2 SDRAM REGISTERED, w/PLL DRAM DIE OPTIONS: * SAMSUNG: C-Die, will move to E-Die Q2'06 * MICRON: U37: B-Die
WV3HG64M72EER-D6
ADVANCED
Revision History Rev #
Rev 0 Rev 1
History
Created 1.0 Moved to Advanced
Release Date
August 2006 August 14 2006
Status
Concept Advanced
August 2006 Rev. 1
11
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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